This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AXI slave design and verification

Please let me know that how to design AXI slave and do its verification? If we design AXI slave using system verilog(its hdl part) then for verification what do we need to write ?I mean master would be as VIP? and How do we verify please give a general idea in steps.