cortex a53 : How to detect cached data is invalid ? (use ddr memory)

a53 core have L1, L2 cache and it is used for read/write data between cpu core and ddr memory.

i don't know if other hardware (such as FPGA) write data to ddr memory, how to detect data was modified.

i tested this problem. (use xilinx ZYNQ MPSoC)

1. ARM : write some random data.

2. read data region for caching.

3. FPGA DMA module: transfer these data to DDR memory region by AXI bus.

4. ARM : read transferred data region.

i think read data on step 4 is cached data on step 2, if it couldn't detect ddr data was changed.

but, test result tell me cache is updated. write data/ read data was identical.

of course all read data cache may be removed other data transition, but there is no fault (read/write data was differ) in a long time test.

So my question is DDR data was changed other H/W by data bus(just AXI bus, not CCI), cache controller can detect it ?

or cache controller continuously monitoring DDR memory data which stored in cache?

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  • If the DMA is hardware coherent with CPU cache in your SoC system, then yes, step 4 can find the data is changed. Otherwise, CPU software will need to perform

    DC IVAC, X1 ; ensure cache is not dirty. A clean operation could be used
    ; but as the DMA will subsequently overwrite this region an
    ; invalidate operation is sufficient and usually more efficient
    DMB SY ; ensures cache invalidation is observed before the next store
    ; is observed
    STR W0, [X3] ; sends flag to external agent
    WAIT_ACQ ([X4]==1) ; waits for a different flag from an external agent
    LDR W5, [X1]

    to get the updated data by DMA.

Reply
  • If the DMA is hardware coherent with CPU cache in your SoC system, then yes, step 4 can find the data is changed. Otherwise, CPU software will need to perform

    DC IVAC, X1 ; ensure cache is not dirty. A clean operation could be used
    ; but as the DMA will subsequently overwrite this region an
    ; invalidate operation is sufficient and usually more efficient
    DMB SY ; ensures cache invalidation is observed before the next store
    ; is observed
    STR W0, [X3] ; sends flag to external agent
    WAIT_ACQ ([X4]==1) ; waits for a different flag from an external agent
    LDR W5, [X1]

    to get the updated data by DMA.

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