some question about ACE

Hi all:

I'm reading ACE protocol. I have some questions about such scenario:

two cache masters (master 0/1) and main meomry are connected by Coherent interconnect.

master 0 and master 1 are both SharedClean.

cacheline size : 64bytes.

Q1: if master 1 writes to portion of the shareable cacheline(update the 1st byte of cacheline),

result 1: master 1 will issue CleanUnique and ,  master 1 cache state become UniqueDirty.

result 2 :master 1 cache state become SharedDirty, master 0 cache state will still be SharedClean.

which result will be right?

Q2: if result 2 in Q1 is right and then master 0 updates the 3rd byte of cacheline,  how the 2 masters and interconnect act?



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