hi,
I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.
Could you give me any suggestion about cache invalid? Thanks!
The program is:
mov x0, #0xffff adr x1, label str x0, [x1] dsb sy isb ...enable MMU and D-cache mov x0, #0xaa55 adr x1, label str x0, [x1] dsb sy isb bl cache_invalid_all (or use "dc ivac, x1") isb adr x1, label ldr x0, [x1] ==> The "X0" value is 0xaa55, the cache invalid seems not work?? .align 6 label: .quad 0
Nothing is stopping the CPU from writing the cache line back to memory after the initial store and before the invalidate. Caches can evict data and write it back to main memory at any time after the store has happened, so your experiment is based on an incorrect assumption and not guaranteed to return the result you expect.
HTH, Pete
Just adding to Pete's post....
The specific bit of the Architecture Reference Manual which states this is:
D3.4.1 General behavior of the caches...The following principles apply to the behavior of caches:...* Any memory location is not guaranteed to remain incoherent with the rest of memory.
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