AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

Hi guys,

I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

First consider an unaligned access on address 0x1.

Can this access be created in 2 ways?

1) Addr=0x0, Wrstrb=1110

2) Addr=0x1, Wrstrb=0111

In the second question consider an aligned access to address 0x0 with 3 incremental bursts, awsize=32-bit.

Is it possible, that only parts of these 3 accesses get written due to a strobe pattern like the following: 1011 0010 0011

Thank you in advance!

Best regards,

Martin

Parents
  • Hi Martin,

    I'll reply to your message in pieces to try and make sure I cover everything;

    1) Addr=0x0, Wrstrb=1110

    This access is correct and works. This type of access is actually mentioned in the AXI specification as one way of doing unaligned transfers ("provide an aligned address and use the byte lane strobes to signal the unaligned start address").

    2) Addr=0x1, Wrstrb=0111

    This is not a valid transaction. The address is unaligned this time, but you cannot set the write strobe of the bottom byte in this situation. Assuming you want to write to bytes 0x1, 0x2 and 0x3, then the correct unaligned transaction would be an address of 0x1 and byte strobes of 1110.

    In the second question consider an aligned access to address 0x0 with 3 incremental bursts, awsize=32-bit.

    Is it possible, that only parts of these 3 accesses get written due to a strobe pattern like the following: 1011 0010 0011

    Yes, this is entirely possible and not unusual - the write strobes in a burst can change for each data transfer.

    It may interest you to have a look at the AXI specifications - these have good descriptions of unaligned AXI transfers, and show a number of examples to help clarify the concept.

    Hope this helps,

    Dave

Reply
  • Hi Martin,

    I'll reply to your message in pieces to try and make sure I cover everything;

    1) Addr=0x0, Wrstrb=1110

    This access is correct and works. This type of access is actually mentioned in the AXI specification as one way of doing unaligned transfers ("provide an aligned address and use the byte lane strobes to signal the unaligned start address").

    2) Addr=0x1, Wrstrb=0111

    This is not a valid transaction. The address is unaligned this time, but you cannot set the write strobe of the bottom byte in this situation. Assuming you want to write to bytes 0x1, 0x2 and 0x3, then the correct unaligned transaction would be an address of 0x1 and byte strobes of 1110.

    In the second question consider an aligned access to address 0x0 with 3 incremental bursts, awsize=32-bit.

    Is it possible, that only parts of these 3 accesses get written due to a strobe pattern like the following: 1011 0010 0011

    Yes, this is entirely possible and not unusual - the write strobes in a burst can change for each data transfer.

    It may interest you to have a look at the AXI specifications - these have good descriptions of unaligned AXI transfers, and show a number of examples to help clarify the concept.

    Hope this helps,

    Dave

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