what is the Instruction L1 TLB and L2 TLB size?

if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.

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  • TLB entry is not the same as cache, so it is not necessary the same size as cache line size. The TLB entry format could differ from one CPU to another. Usually, software does need to know the TLB entry format, unless doing some debugging on MMU issues.

    You might refer to section 'A6.6.2 Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data ' of Cortex-A78 TRM  for information of  L1 TLB format.

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  • TLB entry is not the same as cache, so it is not necessary the same size as cache line size. The TLB entry format could differ from one CPU to another. Usually, software does need to know the TLB entry format, unless doing some debugging on MMU issues.

    You might refer to section 'A6.6.2 Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data ' of Cortex-A78 TRM  for information of  L1 TLB format.

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