if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.
You are talking of which CPU? Or chip?
This is the "core" not the chip/SoC. E.g. core: Cortex-M4, SoC/Chip STM32F469
I'm talking about the TLB of MMU in core, TLB has ITLB, i want to know the size
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