Are 128 bits atomic accesses possible with Cortex-A35?


I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions). I can control the code on both producer and consumer ends. ARMv8-A Reference Manual §B2.2 "Atomicity in the ARM architecture" seems to say only 64 bits atomic accesses are possible.

I can turn off the cache of that data region if it would allow to perform 128 bits atomic accesses.

If not, then isn't that a pity considering the external Cortex-A35 cluster bus width is 128 bits? I can understand 256 bits atomicity wouldn't be possible because it would require 2 AXI4 transactions on the system bus. But since the bus allows for 128 bits accesses, I am wondering why having them atomic wouldn't be possible.



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