could you tell me whether cortex-A55 support cache lock function?
which cache support it, L1 or L2 or L3 or all of them?
What tells you the reference manual?
from its reference manual, I could not get the description of cache lock-down feature, could you help to confirm and check, thanks a lot.
Let's put it like this: If the TRM does not mention/describe cache locking than it is very likely that it is not possible.
thanks a lot, but could you tell me how to get official reply?
Are you still looking for help with this?
yes, it still troubles me , so could you help to confirm it, thanks a lot!
As i could read on some forum, it's depend on some board's timer definition. You must be sure of using the common one. The Arch timer definition (A55 definition in your case) in place of the board's one.In some case, this is locking some cache function.
could we have some information about your environement.Regards
What is the relation of the arch timer and cache locking?
Hi 42Bastian SchickIndeed for me either it has nothing to do. But there will appear to be an impact on this point.I just report what i have read to this subject, may be, it's a wrong track...
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