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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Disable Cache L1 et L2 Armv8</title><link>https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/48070/disable-cache-l1-et-l2-armv8</link><description> Hi 
 I work with the ARMV8 architecture, I want to disactivate L1 cache , 
 to disable the L1 cache I found in the user manual &amp;quot;&amp;quot; The SCTLR.I bit enables or disables the L1 instruction cache. &amp;quot;&amp;quot; 
 my question here is: I did not find in the manual how</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168716?ContentTypeID=1</link><pubDate>Thu, 19 Nov 2020 14:30:20 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:27b268f2-c1b2-42e5-a86c-88e8e5b09691</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;C=0, I = 0 =&amp;gt; no cache at all&lt;/p&gt;
&lt;p&gt;C=1, I = 0 =&amp;gt; L1 data cache is enabled and L2 caches only data.&lt;/p&gt;
&lt;p&gt;C=0, I = 1 =&amp;gt; only L1 instruction cache is enabled.&lt;/p&gt;
&lt;p&gt;C=1, I =1 =&amp;gt; L1 data/instruction cache and L2 unified cache enabled.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168712?ContentTypeID=1</link><pubDate>Thu, 19 Nov 2020 11:35:09 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e3b7723e-2047-4932-9313-b7e265c49401</guid><dc:creator>Rifakst</dc:creator><description>&lt;p&gt;that means if i want to disactivate the L1 cache I can only disable the instruction cache the I bit, and I cannot disable the L1 data cache?&lt;br /&gt;and to deactivate the L2 cace I deactivate the C bit,&lt;br /&gt;I who is not clear to me the L1 cache is a separate cache, so how can we not deactivate the L1 data cache?&lt;br /&gt;and if the C bit also deactivates the L1 data cache, it is worth saying that I cannot deactivate the L2 cache and only activate the L1 cache because from what I understood that if I deactivate the C bit it will disable L1&amp;#39;s Data Cache too&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168706?ContentTypeID=1</link><pubDate>Wed, 18 Nov 2020 16:41:16 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:229390e6-28be-4f22-987d-8d4892dc8cd2</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;My guess (no prove found so far): The L2 cache is a unified cache. Therefore does the C bit control both caches and the I bit only the L1 cache.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168704?ContentTypeID=1</link><pubDate>Wed, 18 Nov 2020 13:32:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:bb77b30e-f763-4772-800c-ffb1b6f9d266</guid><dc:creator>Rifakst</dc:creator><description>&lt;p&gt;Hi &lt;a href="/members/vstehle" class="internal-link view-user-profile"&gt;vstehle&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;thank you for your reply,&lt;br /&gt;can you explain me more please,&lt;br /&gt;in the doc of armV8 cortex A72, I found for the L1 instruction cache it must to disable the I bit of SCTLR register&lt;br /&gt;and to disable the L2 cache must Disable the C bit.&lt;/p&gt;
&lt;p&gt;I didn&amp;#39;t understand how the C bit of register SCTLR can disable the L2 cache and the L1 data cache?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168703?ContentTypeID=1</link><pubDate>Wed, 18 Nov 2020 13:17:22 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:08ac6b29-5e51-473a-9e1e-8ea6789b911a</guid><dc:creator>vstehle</dc:creator><description>&lt;p&gt;Hi &lt;a href="/members/rifakst" class="internal-link view-user-profile"&gt;Rifakst&lt;/a&gt;,&lt;/p&gt;
&lt;p&gt;The&amp;nbsp;&lt;a href="https://developer.arm.com/documentation/100095/0003/system-control/aarch64-register-descriptions/system-control-register--el1"&gt;SCTLR_EL1&lt;/a&gt;&amp;nbsp;bit C a&lt;span&gt;llows to turn off all data cache levels.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;It is similar to I but for data.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168700?ContentTypeID=1</link><pubDate>Wed, 18 Nov 2020 10:04:13 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:5e69163d-e5f9-4e89-bebe-16e88dfd77ea</guid><dc:creator>Rifakst</dc:creator><description>&lt;p&gt;thank you for your reply,&lt;br /&gt;I find nothing about disabling L1 data cache&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Disable Cache L1 et L2 Armv8 cortexA72</title><link>https://community.arm.com/thread/168689?ContentTypeID=1</link><pubDate>Tue, 17 Nov 2020 19:14:04 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:f4d40d2e-1949-46d8-98ab-46d76d3ad9be</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;I recommend to read the cortex-a programmers guide(check Arm docu). It explains all this and more.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>