I work with the ARMV8 architecture, I want to disactivate L1 cache ,
to disable the L1 cache I found in the user manual"" The SCTLR.I bit enables or disables the L1 instruction cache. ""
my question here is: I did not find in the manual how to disable the L1 data cache, so how I can disable the L1 data cache?
I recommend to read the cortex-a programmers guide(check Arm docu). It explains all this and more.
thank you for your reply,I find nothing about disabling L1 data cache
The SCTLR_EL1 bit C allows to turn off all data cache levels.
It is similar to I but for data.
thank you for your reply,can you explain me more please,in the doc of armV8 cortex A72, I found for the L1 instruction cache it must to disable the I bit of SCTLR registerand to disable the L2 cache must Disable the C bit.
I didn't understand how the C bit of register SCTLR can disable the L2 cache and the L1 data cache?
My guess (no prove found so far): The L2 cache is a unified cache. Therefore does the C bit control both caches and the I bit only the L1 cache.
that means if i want to disactivate the L1 cache I can only disable the instruction cache the I bit, and I cannot disable the L1 data cache?and to deactivate the L2 cace I deactivate the C bit,I who is not clear to me the L1 cache is a separate cache, so how can we not deactivate the L1 data cache?and if the C bit also deactivates the L1 data cache, it is worth saying that I cannot deactivate the L2 cache and only activate the L1 cache because from what I understood that if I deactivate the C bit it will disable L1's Data Cache too
C=0, I = 0 => no cache at all
C=1, I = 0 => L1 data cache is enabled and L2 caches only data.
C=0, I = 1 => only L1 instruction cache is enabled.
C=1, I =1 => L1 data/instruction cache and L2 unified cache enabled.
So do I need to do cache flush or anything else before set the C/I bit? or just set the C/I bit during the initialization of cache?
thanks in advance.