On a power up, the SoC asserts some reset signal to the Cortex A processor and it ends up generating an exception. The exception vector on the just powered up processor is implementation defined, but as I've made some reasearch and fount it can be on address 0 or 0xFFFF_0000. Which of the previous addresses is used depends on the VINITHI[CN:0] signal (at least on a Cortex-A53). This is the sequence for a cold boot. The address actually used might be read through the RVBAR_ELn register.
Now, given that a normal VBAR pointed exception vector table has a format so that it's possible to differentiate the exception by Synchronous, IRQ, etc., what is the format of the reset vector table? Is it just a sequence of instructions, because if so, the SoC would put the boot firmware in a ROM addressed (for example) at 0xFFFF_0000, right?
I recommend to read the Armv8-A and Cortex-A53 manual. It all explains what is going on upon reset ( and more).