Does AX4 support burst sizes larger than the bus width?
Narrow transactions are allowed, but do wider transactions also work?
It is not allowed. In "A3.4.1 Address structure" chapter in "AMBA® AXI™ and ACE™ Protocol Specification AXI3™, AXI4™, and AXI4-Lite™ ACE and ACE-Lite™ (ARM IHI 0022E (ID022613))" , the burst size is noted as the followings.
If the AXI bus is wider than the burst size, the AXI interface must determine from the transfer address which byte
lanes of the data bus to use for each transfer. See Data read and write structure on page A3-52.
The size of any transfer must not exceed the data bus width of either agent in the transaction.
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