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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Cortex A-35 prevent fetch code allocation in cache</title><link>https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/47699/cortex-a-35-prevent-fetch-code-allocation-in-cache</link><description> Hi, 
 
 I&amp;#39;m currently working on the i.MX8QX which contains a cluster of 4 A-35 cores. From my understanding, it is possible to prevent data cache allocation using the write or read allocate. From: 
 https://developer.arm.com/documentation/den0024/a</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Cortex A-35 prevent fetch code allocation in cache</title><link>https://community.arm.com/thread/167756?ContentTypeID=1</link><pubDate>Mon, 28 Sep 2020 09:59:22 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:1dc8dc10-762c-4250-9217-7d215113b61e</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;Hello David,&lt;/p&gt;
&lt;p&gt;From my understanding you want to prevent instruction to being allocated and stored in both L1 and L2 caches.&lt;/p&gt;
&lt;p&gt;That can be done at the MMU page level, by configuring the attributes of the page where your code is stored in DDR as inner non-cacheable and/or outer non-cacheable. Inner cacheability is for L1 instruction cache, and outer cacheability is for L2 cache.&lt;/p&gt;
&lt;p&gt;You may want to force the section of your code to be section (1MB) or page (4KB) aligned in your linker script.&lt;/p&gt;
&lt;p&gt;If you are worried about only specific piece of code, make sure to isolate it in a specific text section within your linker script. So that only this text section will be non-cacheable.&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Florian&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex A-35 prevent fetch code allocation in cache</title><link>https://community.arm.com/thread/167692?ContentTypeID=1</link><pubDate>Fri, 25 Sep 2020 14:01:10 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:fbd49c5e-cebf-4522-a9e0-8b6d5c224911</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;IIRC, L2 is unified. You can try cash coloring. But I am not sure if it works for i-cache as well.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex A-35 prevent fetch code allocation in cache</title><link>https://community.arm.com/thread/167669?ContentTypeID=1</link><pubDate>Thu, 24 Sep 2020 16:17:26 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:ff6d90ab-0f3b-474a-be84-f52abf494861</guid><dc:creator>Etienne Alepins</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;The idea would be to lock the L2 data cache to prevent interferences on other cores or subsequent processes, and for the instructions, either also lock the L1 &amp;amp; L2 caches or only lock the L2 and let the L1 fetch and allocate code. The process would also least benefit from the current data/instruction contents in L2 cache. The idea is to not alter L2 and hence not impact execution time of other cores and other processes of current core.&lt;/p&gt;
&lt;p&gt;&amp;Eacute;tienne&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex A-35 prevent fetch code allocation in cache</title><link>https://community.arm.com/thread/167644?ContentTypeID=1</link><pubDate>Thu, 24 Sep 2020 07:33:10 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:448670c1-dfea-4bd2-ac35-f6319af0b85b</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;No. What would be the benefit of just reading one instruction from main memory?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>