Cortex A-35 prevent fetch code allocation in cache

Hi,

I'm currently working on the i.MX8QX which contains a cluster of 4 A-35 cores. From my understanding, it is possible to prevent data cache allocation using the write or read allocate. From: 

https://developer.arm.com/documentation/den0024/a/caches/cache-policies

The cache policies enable us to describe when a line should be allocated to the data cache and what should happen when a store instruction is executed that hits in the data cache.

The cache allocation policies are:

Write allocation (WA)

A cache line is allocated on a write miss. This means that executing a store instruction on the processor might cause a burst read to occur. There is a linefill to obtain the data for the cache line, before the write is performed. The cache contains the whole line, which is its smallest loadable unit, even if you are only writing to a single byte within the line.

Read allocation (RA)

A cache line is allocated on a read miss

Is there a similar parameter to prevent allocation in the instruction cache from fetch code ? 

Kind Regards,

David

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  • Hello David,

    From my understanding you want to prevent instruction to being allocated and stored in both L1 and L2 caches.

    That can be done at the MMU page level, by configuring the attributes of the page where your code is stored in DDR as inner non-cacheable and/or outer non-cacheable. Inner cacheability is for L1 instruction cache, and outer cacheability is for L2 cache.

    You may want to force the section of your code to be section (1MB) or page (4KB) aligned in your linker script.

    If you are worried about only specific piece of code, make sure to isolate it in a specific text section within your linker script. So that only this text section will be non-cacheable.

    Regards,

    Florian

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  • Hello David,

    From my understanding you want to prevent instruction to being allocated and stored in both L1 and L2 caches.

    That can be done at the MMU page level, by configuring the attributes of the page where your code is stored in DDR as inner non-cacheable and/or outer non-cacheable. Inner cacheability is for L1 instruction cache, and outer cacheability is for L2 cache.

    You may want to force the section of your code to be section (1MB) or page (4KB) aligned in your linker script.

    If you are worried about only specific piece of code, make sure to isolate it in a specific text section within your linker script. So that only this text section will be non-cacheable.

    Regards,

    Florian

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