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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Cortex-A8 debug issues</title><link>https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/47615/cortex-a8-debug-issues</link><description> Hi expert 
 Since I debug AM3354(Cortex-A8 Core)， I want to enable IRQ， so I write the assembler code: 
 
 and I put a break point in 
 
 and I run the program in full speed, then stop in MSR CPSR_c, then I run the program again, 
 but the program come</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Cortex-A8 debug issues</title><link>https://community.arm.com/thread/167453?ContentTypeID=1</link><pubDate>Fri, 11 Sep 2020 14:46:38 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:90628c1d-6930-4210-92be-5f92cd32bb25</guid><dc:creator>vstehle</dc:creator><description>&lt;p&gt;Hi &lt;a href="/members/jackshan" class="internal-link view-user-profile"&gt;JackShan&lt;/a&gt;,&lt;/p&gt;
&lt;p&gt;The MSR instruction should&amp;nbsp;not cause an abort, but maybe servicing a pending interrupt immediately after unmasking causes the&amp;nbsp;abort exception?&lt;/p&gt;
&lt;p&gt;You might want to look at the SCTLR and&amp;nbsp;VBAR registers.&lt;/p&gt;
&lt;p&gt;Also, you can determine the vector from the exception PC, which&amp;nbsp;will tell you if this is a data abort or a prefetch abort exception.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Vincent.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex-A8 debug issues</title><link>https://community.arm.com/thread/167451?ContentTypeID=1</link><pubDate>Fri, 11 Sep 2020 11:39:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:820c41dc-79b7-43f3-9d9b-f89442ce459f</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;LR is the &amp;quot;return address&amp;quot;. But different meaning in different modes. Please check the respective chapters on exceptions in the ARM manual(s).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex-A8 debug issues</title><link>https://community.arm.com/thread/167439?ContentTypeID=1</link><pubDate>Fri, 11 Sep 2020 07:32:40 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7ea0d31a-a265-4d99-91c8-365e7c2d6f5a</guid><dc:creator>JackShan</dc:creator><description>&lt;p&gt;How can I check LR whether it is in abort mode? I think LR value is just include an address, right?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Cortex-A8 debug issues</title><link>https://community.arm.com/thread/167438?ContentTypeID=1</link><pubDate>Fri, 11 Sep 2020 07:27:12 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:52e1dece-d5b0-4d47-9a6b-1c250bf4b636</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;1) Check LR in abort mode, where the abort really happend.&lt;/p&gt;
&lt;p&gt;2) &amp;quot;move pc,lr&amp;quot; is a bad idea. Rather use &amp;quot;bx lr&amp;quot; It will cope with mode change.&lt;/p&gt;
&lt;p&gt;3) What happens w/o breakpoint?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>