Since I debug AM3354(Cortex-A8 Core)， I want to enable IRQ， so I write the assembler code:
MRS R0, CPSR ; Pickup current CPSR
BIC R0, R0, #0X80 ; Clear interrupt lockout bits in CPSR
MSR CPSR_c, R0 ; Setup new CPSR value
MOV pc, lr ; back
and I put a break point in
and I run the program in full speed, then stop in MSR CPSR_c, then I run the program again,
but the program come to hard fault immediately.
I am sure the program run to error immediately, even not come to MOV pc, lr.
So I check the CPSR register's bits value,
Bit7(IRQ set bit is cleared) .
It is really confused me a long time, ARM Mode is 10111(ABT mode), and I can change IRQ(bit 7)from 1 to 0, then the program
come to error immediately , why this happen? I really need your help.
1) Check LR in abort mode, where the abort really happend.
2) "move pc,lr" is a bad idea. Rather use "bx lr" It will cope with mode change.
3) What happens w/o breakpoint?
How can I check LR whether it is in abort mode? I think LR value is just include an address, right?
LR is the "return address". But different meaning in different modes. Please check the respective chapters on exceptions in the ARM manual(s).
The MSR instruction should not cause an abort, but maybe servicing a pending interrupt immediately after unmasking causes the abort exception?
You might want to look at the SCTLR and VBAR registers.
Also, you can determine the vector from the exception PC, which will tell you if this is a data abort or a prefetch abort exception.
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