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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>MMU table management during CPU mode switch</title><link>https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/47562/mmu-table-management-during-cpu-mode-switch</link><description> Hello, 
 I have been working on developing comprehensive Data Abort and Prefetch Abort handlers for our ARM Cortex A9 dual-core CPU. 
 Among the exceptions which are covered by these handlers, I am now trying to develop the part related to DDR ECC uncorrectable</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167374?ContentTypeID=1</link><pubDate>Wed, 09 Sep 2020 07:48:06 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:cddb4d4e-3d13-4228-adcc-51098e1a22a5</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;Is that an answer?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167373?ContentTypeID=1</link><pubDate>Wed, 09 Sep 2020 06:10:11 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:e58ff68f-05ea-48c7-8c58-bb4ca89e7909</guid><dc:creator>Nichollast</dc:creator><description>&lt;p&gt;&lt;span&gt;My bare metal application runs in CPU system mode. The Data Abort handler runs in CPU Abort mode. The&amp;nbsp;general purpose registers&amp;nbsp;&lt;/span&gt;&lt;span&gt;{r0-r3,r12,lr}&lt;/span&gt;&lt;span&gt;&amp;nbsp;are saved and restored when switching &lt;a href="https://mcdvoice.me/"&gt;McDVOICE&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167369?ContentTypeID=1</link><pubDate>Tue, 08 Sep 2020 18:50:16 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:a358914e-ee33-4b8d-9d0b-1749f6e69e8b</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;This did not seem to help. So I am just working with the static inline Xil_Out32 functions.... I also implemented error injection for MMU Page Table Entry and instruction using this flow, but one must makes sure that no extra read or write to DDR is done between ECC is disabled and then re-enabled except the injection write.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167314?ContentTypeID=1</link><pubDate>Fri, 04 Sep 2020 21:04:53 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:aa4e855c-43ff-4a89-9e03-d3947ce5e338</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;Shall dramps_DisableECC and dramps_EnableECC be defined in header file dramps.h? so that their types will be static inline?&lt;/p&gt;
&lt;p&gt;That&amp;#39;s the only usage I became aware of and which is compatible with a shareable low-level driver philosophy...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167313?ContentTypeID=1</link><pubDate>Fri, 04 Sep 2020 20:56:26 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:289d6b40-60f0-4051-8ca9-c1d38b85294e</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I have narrowed down the issue to one thing:&lt;/p&gt;
&lt;p&gt;I have developed a low-level driver for DDR controller as dramps.c and dramps.h files.&lt;/p&gt;
&lt;p&gt;Within these files I have declared and defined dramps_DisableECC and dramps_EnableECC functions, which themselves use a static inline function Xil_Out32 function to write to the DDRC registers.&lt;/p&gt;
&lt;p&gt;In the main.c file of my bare metal test I call &lt;span&gt;dramps_DisableECC and dramps_EnableECC functions&lt;/span&gt;. They are plain public void functions.&lt;/p&gt;
&lt;p&gt;When I call dramps_EnableECC and dramps_DisableECC in the main, I end up with additional DDR ECC uncorrectable error either catched by the Data Abort Handler or the Prefetch Abort Handler....&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;But if I use the Xil_Out32 function directly within the main.c, I don&amp;#39;t get these extra aborts....&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;So I came to the conclusion that I needed to define dramps_DisableECC and dramps_EnableECC function as static inline function... My guess is that not using inline function implies that calling these functions will result in a jump to a different MMU section, thus requiring MMU to load a new Page Table Entry and maybe evicting another...&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I still want to keep a separate low level driver with dramps.c and dramps.h files.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;How would you suggest me to implement that?&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Thank a lot for any help.&lt;/p&gt;
&lt;p&gt;Florian&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: MMU table management during CPU mode switch</title><link>https://community.arm.com/thread/167309?ContentTypeID=1</link><pubDate>Fri, 04 Sep 2020 14:21:08 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:3a4d7b1a-2224-4cb1-b4e4-e2f684dd5772</guid><dc:creator>flongnos</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I found out why I had a MMU translation error. The reason was that I provided the DRAM physical address for the stuck bit check. So the untranslated address hits in MMU page with NO_ACCESS attribute (AP[1:0] = 0x0).&lt;/p&gt;
&lt;p&gt;Actually the DDR controller only reports physical address of the DDR ECC uncorrectable error, but not the logical AXI address.&lt;/p&gt;
&lt;p&gt;As a result I developed translation function to convert the reported physical address into an AXI logical address.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;However I have another exception right after re-enabling DDR ECC, and before reading out the corrupted cacheline:&lt;/p&gt;
&lt;p&gt;The error address is in the last section of the bare metal program...&lt;/p&gt;
&lt;p&gt;Even when I do nothing between disabling and re-enabling ECC, I still get this exception...&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Florian&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>