<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Invalidate queue</title><link>https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/47552/invalidate-queue</link><description> Hi 
 Does a55 have an invalidate queue? 
 Is it necessary that executing dmb before access shared variable in an SMP system? </description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>RE: Invalidate queue</title><link>https://community.arm.com/thread/167232?ContentTypeID=1</link><pubDate>Mon, 31 Aug 2020 14:50:30 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7350154f-a170-4012-aa6c-9b89cb7180e5</guid><dc:creator>42Bastian Schick</dc:creator><description>&lt;p&gt;Depends on the memory type. Cached or strongly ordered. In case you are not sure use it. Also I recommend the cortex-a programmers guide.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>