How to test L1/L2 cache?


Can anyone tell me if it is possible to test L1/L2 cache for Cortex A55?

In the spec, L1 cache can be directly accessed in EL3. However, I hope I can do some memory test for the L1/L2 cache in EL1.

Is there a way to do that and how?


-Zhiping Jiang

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