Can anyone tell me if it is possible to test L1/L2 cache for Cortex A55?
In the spec, L1 cache can be directly accessed in EL3. However, I hope I can do some memory test for the L1/L2 cache in EL1.
Is there a way to do that and how?
Thank you, Sujun.
But what I want to do is to verify the L1/L2 cache like to verify any other memory parts. In other words, I hope I can write some pattern, say all '0' or 'F' to the cache and read back and compare to see if there is any difference (failure).
So far, I can be sure that we can do this in EL3 for L1. But I didn't see any post for L2 cache.
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