Which PMU Events for L2 Cache Misses on Cortex-A72


I want to monitor L2 cache misses through Linux perf, i.e. data that is not in the L2 cache and requires a main memory access, but I'm a bit confused which PMU events to use.

The Cortex-A72 TRM lists the following which seem likely candidates:


Which is a L2 cache miss?

What I'm trying to do is measure the effect of the L2 cache size on the performance of a CPU with 0.5MB L2 cache vs that of CPU with 1.0MB L2 cache.

Kind regards

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