Hello. I just found some information about speculative execution and speculative loads/cache line-fills on some ARM processors. Unfortunately I wasn't able to find if any of these present on Cortex-A5. I only saw it has an in-order execution pipeline, but not sure it is excluding. Does A5 implement some kind of speculative execution?
And here is the problem motivating this question:
We have an A5 - based system with a complex memory subsystem. Some parts of the memory are not ready by the time A5 is already up and running. Here is a problematic flow:
1) A5 is mapping a certain memory region R as Normal and cacheable memory when it is not yet accessible
2) ...some complex code is executed, but no explicit access to R is made
3) The memory becomes accessible
I am observing an issue in step (2) - and using hardware tools it appears that a read access to R is seen by the hardware - and it looks like the addresses are at addresses on cache line boundaries
So the question is - could be that during step (2) A5 is executing some kind of speculative load in R - as it is already mapped? Or such a scenario is not possible on A5?
Not sure, but a hint could be the event counter:
"Data write architecturally executed. Counts the number of data write instructions accepted by the Load Store Unit. This includes counting the speculative and aborted STR/STM, and the writes because of the SWP instructions."