In trustzone technology, world switching between rich and secure worlds may occur when 1)invoke a trust application 2)insecure interruption interrupts the execution in secure world.
However, cache coherence may be an issue in this procedure as usually (or just in my soc) L1 cache uses write-back policy.
I'm curious about would and How arm/trustfirmware deal with this?
By just clear and invalidate the whole L1 Data/Instruction cache? If so, doesn't it degrade the performance so much?
Any idea would be helpful and looking forward to discuss with you ;)
The NS-bit is part of the cache tag. So in general you do not have to care about the caches.
Is the NS-bit implemented in L1 cache tags only, or both cache lines in L1 and L2 cache?
In CPUs with Trustzone support, each cache line (including L1, L2, L3 cache) is tagged with Secure or Non secure state when it was allocated from secure or non secure memory. Trustzone technology will guarantee that code running in CPU non secure state cannot access cache line in secure state. Also for system cache that supports Trustzone, it is the same.
So software does not need to flush cache when switching between secure and non secure state.
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