Would and How arm/trustfirmware take care of cache coherence in trustzone technology?

In trustzone technology, world switching between rich and secure worlds may occur when 1)invoke a trust application 2)insecure interruption interrupts the execution in secure world.

However, cache coherence may be an issue in this procedure as usually (or just in my soc) L1 cache uses write-back policy.

I'm curious about would and How arm/trustfirmware deal with this?

By just clear and invalidate the whole L1 Data/Instruction cache? If so, doesn't it degrade the performance so much?

Any idea would be helpful and looking forward to discuss with you ;)

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