I have been reading about io coherency and the inner/outer shareability (SH bits in PTE). I kind of understand the concept of both but need help to connect the 2 concepts together. Lets assume a platform with (runs only one OS):
- CCI-400- A53 Cluster - ACE- A57 Cluster - ACE- DMA - ACE-Lite
- The 2 Clusters are in inner shareable domain and all normal memory SH bits is set to inner shareable.- The DMA is in the outer shareable domain.
Now we setup a DMA transfer, allocate Tx and Rx buffers and do the transfer using the io coherency (no cache maintenance). As I understood the Tx and Rx have to be marked outer shareable in their PTE.
So, my question: The PTE is read by the MMU, how does the CCI know that it should snoop the cpu caches for the tx and rx buffers addresses? Does the SCU do some magic for these addresses or maybe the cache is marked?
Hope the question makes sense to you.
Based on the PTEs and some other factors (such as tie-offs) the ACE masters will signal the domain of the transaction on the AxDOMAIN signals for each transaction.
The coherent interconnect can then use the AxDOMAIN information to determine whether a snoop needs to be performed for that transaction. Additional information regarding the kind of shareable transaction is carried on the AxSNOOP channels.
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