Seeking more information on SError on A53 core

Hi,

I am currently trying to understand (and possibly diagnose) a fault that we are seeing on a Cortex A53 CPU within a Xilinx Zync Ultrascale MPSoC FPGA.  The problem occurs when firmware (bare metal) performs PCI express enumeration.  The core SError faults when a configuration write access (memory write to SoC peripheral register) is attempted although configuration reads are okay.  Though the problem is very likely to be a hardware problem (these are new prototype boards we have designed and built, of which 2 work fine and 2 give this error), I have found little documentation that describes how SError exceptions occur, beyond the flushing of cache data generating a fault asynchronous to program execution as mentioned in the documentation relating to sync/async exceptions.

developer.arm.com/.../synchronous-and-asynchronous-exceptions

So my question is, is there any more documentation/discussion available from an A53 ARM core perspective on what causes an SError exception? 

Thanks in advance, Kevin.   

Note: I did found a blog article on exception handing that had a link to an ARM forum post which sadly doesn't seem to exist.

community.arm.com/.../re-what-is-serror-detailed-explanation-is-required