• State Accepted Answer
  • Locked Locked
  • Replies 1 reply
  • Subscribers 347 subscribers
  • Views 19206 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Synchronization Between CortexA and CortexM

M.Eladouly

Hello,

I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4).

Currently, I use Load/Store executive assembly instructions along with memory attributes for the MMU to synchronize between the CortexA cores.

My question is, is there a similar technique to synchronize between the A35 cores and the M4 core? Or this is a vendor specific mechanism that shall be used (NXP in our case)?

Thank you.