Hi,
Can a FIXED burst type have AxLEN > 0? If so how should the address increment? How should the WSTRB for each beat specifically for an unaligned start address? The spec says FIXED burst is used for accessing a FIFO, where data width is fixed.
Sorry if this type of question is already asked. A very related question is already here: community.arm.com/.../164179
Thanks,
-Murali
The main feature of a FIXED transaction type is that the address DOES NOT increment between transfers.
So yes, you can have fixed transactions longer than 1 transfer (up to 16 transfers), and the address will be the same for every transfer in that transaction.
Then with an unaligned start address, this restricts the byte lanes that can be used in each transfer (as the address remains unaligned in a fixed transaction) , whereas in an INCR transaction it is only the first transfer that can be unaligned (all others are AxSIZE aligned).
So in a FIXED transaction, if AWSIZE=0x2 (32-bit) and AWADDR=0x1, this means each transfer in this transaction can use any of WSTRB[3:1]. WSTRB[0] will always be 1'b0 because of the unaligned address.
HI,
Regarding to "fixed transactions longer than 1 transfer (up to 16 transfers)", does this apply to both AXI3 and AXI4 ?
Archer
Yes, the changes in AXI4 did not affect FIXED transactions. Only INCR transactions can be longer than 16 transfers in AXI4.