EDSCR err bit set after a write to EDITR

Hi,

I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

So I try to follow that to give the state information.

Cortex-57

JTAG TCK = 3,788MHz.

ARM_STATE_AARCH64 is set

Before Halt state:

EDPRSR = 0x1

EDSCR = 0x03007C02

After Halt state:

EDPRSR = 0x1

EDSCR = 0x03006113

After Write to EDITR with opcode 0xd503201f for a NOP instruction:

EDPRSR = 0x11

EDSCR = 0x03006153

EDSCR differs from the resolved entry in bits HDE=1, RW=0100, EL=1

And Aarch64 has no thumb mode instruction, this does not solve my problem.

Any help is appreciated.

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  • Hi kka,

    This is strange. So the NOP instruction (0xD503201F) should be OK in debug state when the processor is in AA64, according to sec. H2.4.2 of the Arm Arm v8-AR as NOP is explictly listed under the 'A64 instructions that are unchanged in Debug state' sub-section.

    You have HDE set = b1 prior to inserting the instruction into the EDITR so that's ok.

    Do other instructions (e.g. MOV x0,#0xA5  (0xD28014A0)) cause the same error, or is it just the NOP ???

    Such a MOV <immed> instruction is allowed in debug state so it would be interested to know the result.

    Let me know how you are getting on.

    Regards,

    Stuart

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  • Hi kka,

    This is strange. So the NOP instruction (0xD503201F) should be OK in debug state when the processor is in AA64, according to sec. H2.4.2 of the Arm Arm v8-AR as NOP is explictly listed under the 'A64 instructions that are unchanged in Debug state' sub-section.

    You have HDE set = b1 prior to inserting the instruction into the EDITR so that's ok.

    Do other instructions (e.g. MOV x0,#0xA5  (0xD28014A0)) cause the same error, or is it just the NOP ???

    Such a MOV <immed> instruction is allowed in debug state so it would be interested to know the result.

    Let me know how you are getting on.

    Regards,

    Stuart

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