Has anyone come across documentation that tells how to calculate entrance and exit times from low-power modes where the L1 and L2 cache maintain data coherence?
Thanks,
Eric
I had the same thought. I'm using an A35, but, there's so much that's depending on how we're using it, I was just wondering if there was a white paper with guidelines on getting estimates. Thanks for the help.
Even saying you are using an A35 does not help more. Each SoC is different.I wonder, do you fear a competitor will read your post if you disclose the chip you are using?Anyway, some SoC manuals tell you about how many cycles the PLL needs to lock and things like this.And if not the manual, then the chip-vendor might tell you.But the core is the smallest part on your SoC, so the ARM (core) forum will be of little help.