I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue.
When I write data(4 bytes aligned) to pcie bar with ioremap_wc, there is some incorrect data. And it is correct if write data twice. Or I make use of the ioremap which means device_nGnRE attribute.
When I read the armv8 arm, it say that the write of normal_nc is visible for all the observers. I am not sure if the cache maintenance should work. I want to know what is the best practice in these senario. Is there something like flush write buffer helping me flushing data to pcie bar?
There is no coherent between arm cpu and pcie.
As 42Bastian Schick pointed out, this is a DSB that you need here.
See "K11.5.4 Ordering of Memory-mapped device control with payloads" in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for example:
STR W5, [X2] ; data written to the data buffer
STR W0, [X4] ; X4 contains the address of the DMA control register
You mention the PCIe in your system is not coherent so you need a DSB ST (store-store, full system) here.
Thanks. "K11.5.3 TLB maintenance instructions and barriers" seems answer my question. I will try it in my environment.
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