Hello,
I have a multi-core system which implements an L3 cache memory and a memory controller.
In addition, i am using ARM Cortex-A72 MPcores, 2 cores per cluster, several clusters.
I am trying to write a bare-metal application which will hopefully make a maximum number of write and read requests towards the external L3 memory unit,
by running on addresses in a certain order that are not allocated in the L1 and L2 data caches, and thus forcing eviction on each write/read.
I have noticed that disabling the MMU has caused me a memory BW degradation.
However, i am having trouble finding the "best" memory attributes that i should configure the page tables with, which will provide the maximum memory BW i am looking for.
Could somebody perhaps share with me some information about that? or, any useful reference?
Thanks!
Disabling the MMU forces all accesses to be treated as Device nGnRnE which is the most restrictive memory type, and typically has the worst performance. Using Normal Non-cacheable or Normal cacheable memory is likely to give the best bandwidth.