I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference between them, for safety reasons; as instance 256KB for Process1 and 256K for Process 2).
In other words I am looking for a way to exactly know which cache set and ways can be used by a specific process, and ensure that others are not evicted or used during this process execution. That would avoid the need to flush and invalidate, that requires some time.
According to Armv8-A, I spotted the Cache lockdown, but according to some posts on this forum, this feature is rarely implemented on specific cores (and it is not implemented in Cortex-A35).
I also found some techniques:
But I may have missed something in the documentation.
If anyone knows a way of achieving this or knows that is it clearly not possible, that would helpful.
Both L1 and L2 cache are physically indexed, so cache coloring should be possible.
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