I'm having trouble finding any informations on partial neon register dependencies.
Take for example the following code:
ld2 {v0.16b, v1.16b}[0], [x0] ld2 {v0.16b, v1.16b}[1], [x1] ld2 {v0.16b, v1.16b}[2], [x2] ...
Does the second load have to wait for the previous one to complete or may it continue right away?
I'm working with image data that needs to be palletised from a 256 16-bit entry table and I want to further process it with neon. Unfortunately due to the table size are tbl instructions not an option, since it would take up all of the 32 registers. Would doing the look up with arm first, then combining and transfering the results in 4 64-bit registers be faster?
If it helps I'm targeting Cortex-A57.
Hi doofenstein,
Chapter "4.4 Register Forwarding Hazards" of the Cortex-A57 Software Optimization Guide talks about similar cases.
You might want to measure your specific example using the PMUs:
"The Performance Monitor Unit (PMU) in Cortex-A57 may be used to determine when register forwarding hazards are actually occurring The implementation defined PMU event number 0x12C (DISP_SWDW_STALL) has been assigned to count the number of cycles spent stalling due to these hazards."
thank your for answer. Unfortunately I currently don't have access to the PMU on my target device.
Though I want to try implementing both methods I described in my first post and compare how well they fare. I'm especially concerned because of the large amount of instructions. If I want to use the full neon register width, that would be 16 unrolled loads. Additionaly since neon load/store doesn't allow for address generation that would be two additional instructions per load (pull the index byte and combining it with the palette pointer). The alternative method would save the add, but in the end it wouldn't be a lot less instructions, since it would also include packing the loaded halfwords into 64-bit words, transfering them into neon registers and then deswizzling those.