Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU?

The SW_INCR event only counts writes to the PMSWINCR register, not all architecturally executed instructions.

For Cortex-A9, there is no PMU event that counts the architecturally executed instructions. The closest available event is 0x68 as described by song846079 below.

I am using for collecting CPIs. How to read the counter event "SWINCR" ,is there any different with other counter events? And the Armv7 manual says that "PMSWINC is a write-only register
".Dose it mean that I can't read it?

What kind of target are you using?

The Fast Models don't fully model the PMU, and most of the events aren't functional.  Meaning that you get counts of zero.

Thank you. I tried and when I use the SWINCR(in armv7 cortex-a9 is number 0x00  event) to collect information ,I only get 0 every time I read the counter in my experiment,but the other counter event works well,like data cache miss,instruction cache miss...,why?