Given a multiprocessor system, how are the PC values of secondary cores set from the primary core? I've read lots of threads stating it can be done but without any details. I could not find anything in the ARMv8 reference manual.
One might contrive a mailbox system where the secondary cores wfe and check the value of a mailbox address when woken up. But is there a supported method to directly write the secondary core PC before waking it up? What are the various methods for "waking up" a core?
Hi Branden Sherrell,
As an example, Linux permits two different options for waking up secondary cores on "arm64":
- Spin table (write PC to memory)
- PSCI (call hypervisor/firmware)
Thanks for the link! DEN0022A is mentioned in that documentation. I took a look at the PCSI monitor call for CPU_ON but it is described only in a way that one might describe a function call. The implementation seems to be undefined. That said, it seems to be a standardized method for pointing a CPU to an entry point, but its implementation might use a spin table, for example.
It seems overly complicated, in my opinion, to rely on EL3 to enable a CPU. I say that because you will be issuing the SMC from another core. So during the exception handling you would need to signal the available CPU to _also_ execute an SMC instruction so that it can ERET to the appropriate exception level, right? What about CPU_OFF or CPU_SUSPEND? What hardware support is available to implement these calls? This seems to be describing control of secondary CPUs from a primary (or just another) CPU, but you mentioned it was not directly possible?
Maybe the trusted firmware has an implementation example for these. It seems like a hard synchronization problem at first glance. Perhaps I am missing something. Is there an event that can be sent to all cores to send them to EL3 for such a synchronization even? It seems then that with MPIDR one could check its ID and eret to the appropriate PC/EL while all other cores exit immediately.
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