I am working with GICV3 on a Cortex A53 that is currently in aarcH32 EL2 state.
When I try to read the ICC_HSRE I get an undefined instruction and the system crashes.
The instruction I am using is
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
mrc p15, 4, r7, c12, c9, 5
Any idea what is wrong here, and why I get an undefined instruction.
In aarch32 EL2, I am pretty sure this is the register that should be used to access the GIC System Register Enable Register?
One possibility is that you need to set ICC_MSRE.Enable or ICC_SRE_EL3.Enable (depending on whether EL3 in AArch32 or not), as otherwise accesses to ICC_HSRE will be undefined.
Just getting back to this now. Attempts to access ICC_MSRE also fail with an undefined instruction.
Not every SoC has GIC system registers. Which SoC do you use?
i.MX8M. Reading ID_PFR1 indicates that GIC_V3 registers are available?
ID_PFR1 indicates that GIC_V3 registers are available?
You need to "wakeup" the interface IIRC:
/* Wakeup GICR interface */
str w1,[x0,#0x14] // GICR_WAKER
And then enable the system register in the ICC_SRE_EL2/EL3 registers.BTW, it is a GIC-500.
GIC-500? i.MX8M utilises Cortex A53, right? And from the documentation I have to hand for Cortex A53, it all suggests GICV3/GICV4 is the GIC used.
0x38880014 already reads back as 0. I should point out that I am using the CPU is aarch32 bit mode. Accesses to ICC_HSRE and ICC_MSRE (the aarch32 equivalent of ICC_SRE_EL2/EL3 in 32 bit mode) still fail with an undefined instruction error.
Hi PJ Nee,
GIC-500 is an implementation of the GICv3 architecture:
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