I am working with GICV3 on a Cortex A53 that is currently in aarcH32 EL2 state.
When I try to read the ICC_HSRE I get an undefined instruction and the system crashes.
The instruction I am using is
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
mrc p15, 4, r7, c12, c9, 5
Any idea what is wrong here, and why I get an undefined instruction.
In aarch32 EL2, I am pretty sure this is the register that should be used to access the GIC System Register Enable Register?
One possibility is that you need to set ICC_MSRE.Enable or ICC_SRE_EL3.Enable (depending on whether EL3 in AArch32 or not), as otherwise accesses to ICC_HSRE will be undefined.
Just getting back to this now. Attempts to access ICC_MSRE also fail with an undefined instruction.
Not every SoC has GIC system registers. Which SoC do you use?
i.MX8M. Reading ID_PFR1 indicates that GIC_V3 registers are available?
ID_PFR1 indicates that GIC_V3 registers are available?
You need to "wakeup" the interface IIRC:
/* Wakeup GICR interface */
str w1,[x0,#0x14] // GICR_WAKER
And then enable the system register in the ICC_SRE_EL2/EL3 registers.BTW, it is a GIC-500.
GIC-500? i.MX8M utilises Cortex A53, right? And from the documentation I have to hand for Cortex A53, it all suggests GICV3/GICV4 is the GIC used.
0x38880014 already reads back as 0. I should point out that I am using the CPU is aarch32 bit mode. Accesses to ICC_HSRE and ICC_MSRE (the aarch32 equivalent of ICC_SRE_EL2/EL3 in 32 bit mode) still fail with an undefined instruction error.
Hi PJ Nee,
GIC-500 is an implementation of the GICv3 architecture:
Did you try to write those in 64bit mode before switching to AArch32?
Our aarch64 code is written in assembly language (.s), and only executes some basic instructions before switching aarch32.
When I add an mrc call to read ICC_HSRE, I get an "unknown mnemonic" error. I can't find a workaround for this.
The name of the register is different (see above). Using these you should be able to enable the system register interface.At least it works for me, but then, I use AArch64 throughout the whole application.
Ok - I eventually figured out how to access ICC_SRE_EL2 in aarch64 bit mode.
Reading this register returns 0xf in aarch64 bit mode prior to the switch to aarch32.
Reads from ICC_SRE_EL3 produce a "synchronous abort" error (probably not unexpected as system is reports it is in aarch64 EL2 at the time).
The question remains though as to why accesses in aarch32 to ICC_HSRE fail with an undefined instruction error.
ICC_MSRE can only accessed in EL3 (or monitor mode).
Ok. So are you saying I need to switch to EL3 first to be able to set the ICC_MSRE.Enable bit?
And then from that point on I should be able to access ICC_HSRE?
You are starting up in EL3, so you should there enable set the rights for EL2..EL0.
Bastian, this issue is showing up again. When I start up in EL3 (on i.MX8M) it seems I cannot access ICC_SRE_EL2.
If I put the following instruction in to my code I get a crash
mrs x8, s3_4_c12_c9_5
I believe this to be the correct mnemonic to access ICC_SRE_EL2.
I've looked at this every way I can but find a way to make it work. Any ideas?
View all questions in Cortex-A / A-Profile forum