Why the address width of MMU-500 is different with Cortex-A53/57?

I find the description below from MMU-500 TRM.

Address width

The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

bus is 48 bits.

But I know that the AXI address width of Cortex-A53/57 is 44 bits.

So If Cortex-A53/57 and MMU500 are connected with the same CCI-400 interconnect, will CCI-400 ensure the matching of  address width, or will MMU500 only connect 44 bits output address with CCI-400?

And I find that the address width of Cortex-A7/15 and MMU-400 is 40 bits, I am confused about MMU-500.

Would you please kindly explain this? Thanks.

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  • It's to support stage 1 translation.

    The virtual address space in AArch64 is 48 bits (0x0 to 0x0000,FFFF,FFFF,FFFF).  For EL1/0 there is another 48-bit range at the top of the 64-bit range (0xFFFF,0000,0000,0000 to 0xFFFF,FFFF,FFFF,FFFF).

    The figure you quoted (44 bits) is the size of the supported physical address width. 

    When configured to perform stage 1 translation, the SMMU needs to support these address ranges as inputs.

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  • It's to support stage 1 translation.

    The virtual address space in AArch64 is 48 bits (0x0 to 0x0000,FFFF,FFFF,FFFF).  For EL1/0 there is another 48-bit range at the top of the 64-bit range (0xFFFF,0000,0000,0000 to 0xFFFF,FFFF,FFFF,FFFF).

    The figure you quoted (44 bits) is the size of the supported physical address width. 

    When configured to perform stage 1 translation, the SMMU needs to support these address ranges as inputs.

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