A72 not handling IRQ properly

I want a register write to happen whenever there is an interrupt at irq pin of core 0 and I have written the code for the same. A72 branches to address 0x18 (V=0 and VE=0) by default whenever there is an irq interrupt. On this instruction address, instruction to change the program counter to the address of the register write code is present. In the waveform I can see that A72 branches to 0x18, then starts fetching instructions from the address d0. It gets e3a00501 i.e. the opcode for the instruction at d0 address. Now instead of treating this as an instruction, A72 treats this as an address and starts fetching from the address e3a00500. There is no instruction at this address and it gets 00000000 as reply. Now since this is not a valid instruction, it enters into ABORT mode. The following is the code -

00000018: e59ff0b0 ldr pc, [pc, #176] ; 000000d0 <irqhandler>

000000d0 <irqhandler>:

000000d0: e3a00501 mov r0, #4194304 ; 0x400000
000000d4: e24ee004 sub lr, lr, #4
000000d8: e59f11ec ldr r1, [pc, #492] ; 000002d0 <PC_CHANGE_TO_DDR_CPU0+0x8c>
000000dc : e5801000 str r1, [r0]
000000e0: e160006e eret

Am I doing something wrong? Please help !!

More questions in this forum