Out-of-Order of Cortex-A15 core and an interrupt

I would like to know an behaviour of the interrupt on out-of-order.

In-order situation :  The interrupt is issued at once because the instruction that is not completed is discarded.

Out-of-Order situation : The interrupt is not issued until the instruction that is executing is completed. For example,  under the below condition,

calculation instruction

calculation instruction

calculation instruction

                |

calculation instruction

simple instruction

If the simple instruction can bypass many calculation instructions,  the interrupt is not issued until all calculation instructions completed.

Is my understanding right? If my understanding is right, In-Order pipeline is better performance than Out-of-Order pipeline.

How do you think about this?

Best regards,

Michi

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  • It is always tricky to describe how this works and have it apply to all possible situations, simply because the Cortex-A15 and similar ARM processors are very complex devices. At a high level, in an out-of-order pipeline, consider the instruction sequence you show above: even though the simple instruction may have "completed" before the calculation instruction that appears before it in program order, the simple instruction that has "completed" is not yet "retired". What is important to realize is that instructions are "retired" in program order.

    So if an interrupt occurs before the calculation instruction is complete, the exception mechanism can still preempt the calculation instruction; what would happen, though, is that up on returning from the exception, the execution would resume with the calculation instruction that was preempted... which does imply that the simple instruction would execute again. However, this does not cause an issue with the proper function of the instruction sequence.

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  • It is always tricky to describe how this works and have it apply to all possible situations, simply because the Cortex-A15 and similar ARM processors are very complex devices. At a high level, in an out-of-order pipeline, consider the instruction sequence you show above: even though the simple instruction may have "completed" before the calculation instruction that appears before it in program order, the simple instruction that has "completed" is not yet "retired". What is important to realize is that instructions are "retired" in program order.

    So if an interrupt occurs before the calculation instruction is complete, the exception mechanism can still preempt the calculation instruction; what would happen, though, is that up on returning from the exception, the execution would resume with the calculation instruction that was preempted... which does imply that the simple instruction would execute again. However, this does not cause an issue with the proper function of the instruction sequence.

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