I have a question about C/C++ atomic operation on ARM9 and ARM Cortex-M4. I am using ARMCC compiler with C / C++ languages. It interests me if it is possible that an interrupt will be handled in the middle of operations:
Does anything change if you access to these objects indirectly by pointer or reference?
Are there any other basic operations potentially unsafe in multi-thread application?
Thanks for answers.
Good night.
I'm coincidentally studying the behavior of instructions LDM / STM and its variations, but only for Cortex-M0 at the time, and ended up getting a little confused after reading the answers to this post. According to the text on page 136 of the book "The Definitive Guide to the ARM Cortex-M0 (2011)" on the subsection "Use of Multiple Load and Store Instructions", the instructions LDM / STR when interrupted by some ISR return to resume the process from the start, so if making the reading of a value from an address that represents a port FIFO device such values may be requested as a new reading will restarting the entire process.
Now in response to Joseph Yiu, and earlier by jensbauer as quoted below, instructions LDM / STM interrupted when returning execution where they were:
jyiu: If a 64-bit data is accessed using LDM/STM instructions, as Jens said, the instruction can get interrupted in the middle, the processor execute the ISR and then resume the LDM/STM from where it was interrupted. jensbauer: The LDM/STM instructions will be interrupted, and when the interrupt returns, the LDM or STM instruction will continue from where they left off.
jyiu: If a 64-bit data is accessed using LDM/STM instructions, as Jens said, the instruction can get interrupted in the middle, the processor execute the ISR and then resume the LDM/STM from where it was interrupted.
jensbauer: The LDM/STM instructions will be interrupted, and when the interrupt returns, the LDM or STM instruction will continue from where they left off.
And a line below Joseph Yiu says:
If the 64-bit data is accessed using LDRD/STRD instructions, the instruction can get abandoned and restart after the ISR.
This behavior is specific to the Cortex-M3 / 4 controllers? or just the instructions with modifiers "D" is that it has such a behavior?
Also tried to find more information on the book "ARM Assembly Language: Fundamentals and Techniques", especially in chapter 10, in the subtitle: "10.2.1 - LDM / STM Instructions" but have not found anything concrete, which eliminates my doubt.
Who is right? current information? or contained in the book?
Thanks.
Hi Carlos,
Sorry that I forgot to specify that the LDM/STM resume behavior is for ARMV7-M, where ICI/IT bits present in xPSR. (ie Cortex-M3/M4/M7). For ARMv6-M (Cortex-M0/M0+), the LDM/STM are abandoned and restarted after interrupt service.
There are no LDRD/STRD instructions in ARMv6-M.
Regards,
Joseph
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