Using interrupts not implemented as Software interrupts?

We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating the registers SETENA / ClrEnable and SetPend / ClrPend.

For example, being the interrupt # 5 (Exception # 21) not implemented at the hardware level, this could be used as an interrupt / exception of software?

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  • Hi Carlos,

    It depends on which processor you are using:

    In the Cortex-M0, Cortex-M3 and Cortex-M4 processors, a spare interrupt in the middle (e.g. IRQ 0 to 15 implemented, IRQ #5 not used) can still be used by software. The interrupt input pin is tied to 0 but the interrupt pending status and priority logic is still there.

    In the Cortex-M0+ processor, we've added a configuration option for chip designers to remove unused interrupt hardware. Chip designers can choose to use this feature to reduce gate count, or leave the spare interrupt in. You can test by setting the enable bit and see if the read back value is 1.

    One more thing to add about comparing using SVC with using spare IRQs for software interrupt:

    SVCall exception is a synchronous exception. It means the instructions behing the SVC will not get executed and will wait for the SVC handler to complete first.

    If you use IRQ as software interrupt, a couple of instructions after the setting of pending status/enabling of the interrupt could still be executed before entering the ISR. This topic is covered in Application Note

    ARM Cortex-M Programming Guide to Memory Barrier Instructions

    See section 4.5

    ARM Cortex-M Programming Guide to Memory Barrier Instructions: 4.5. Enabling Interrupts using NVIC

    Also, if the IRQ is blocked by PRIMASK or other interrupt masking registers, the program will just continue.  If the SVC is blocked you would get a HardFault. As long as you handle these situations in software, yes, you can use a spare IRQ as software interrupt/exception.

    regards,

    Joseph

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  • Hi Carlos,

    It depends on which processor you are using:

    In the Cortex-M0, Cortex-M3 and Cortex-M4 processors, a spare interrupt in the middle (e.g. IRQ 0 to 15 implemented, IRQ #5 not used) can still be used by software. The interrupt input pin is tied to 0 but the interrupt pending status and priority logic is still there.

    In the Cortex-M0+ processor, we've added a configuration option for chip designers to remove unused interrupt hardware. Chip designers can choose to use this feature to reduce gate count, or leave the spare interrupt in. You can test by setting the enable bit and see if the read back value is 1.

    One more thing to add about comparing using SVC with using spare IRQs for software interrupt:

    SVCall exception is a synchronous exception. It means the instructions behing the SVC will not get executed and will wait for the SVC handler to complete first.

    If you use IRQ as software interrupt, a couple of instructions after the setting of pending status/enabling of the interrupt could still be executed before entering the ISR. This topic is covered in Application Note

    ARM Cortex-M Programming Guide to Memory Barrier Instructions

    See section 4.5

    ARM Cortex-M Programming Guide to Memory Barrier Instructions: 4.5. Enabling Interrupts using NVIC

    Also, if the IRQ is blocked by PRIMASK or other interrupt masking registers, the program will just continue.  If the SVC is blocked you would get a HardFault. As long as you handle these situations in software, yes, you can use a spare IRQ as software interrupt/exception.

    regards,

    Joseph

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