Support for pipelining flops in AXI

Hi All,

Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

Thanks

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  • Hello naveen,

    The AXI protocol is a point-to-point protocol, meaning that it defines the signal behavior between a master interface and a slave interface.

    Due to the timing flexibility in AXI, it is convenient to insert timing elements such as register slices (is that the "pipelining flops in between valid/ready signals" you were talking about?) on a channel.

    A register slice has two interfaces: a slave interface and a master interface, as shown below:

    111.png

    Each interface performs the valid/ready handshaking as per the AXI protocol independently.

    Does the above answer your question?

    Xingguang

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  • Hello naveen,

    The AXI protocol is a point-to-point protocol, meaning that it defines the signal behavior between a master interface and a slave interface.

    Due to the timing flexibility in AXI, it is convenient to insert timing elements such as register slices (is that the "pipelining flops in between valid/ready signals" you were talking about?) on a channel.

    A register slice has two interfaces: a slave interface and a master interface, as shown below:

    111.png

    Each interface performs the valid/ready handshaking as per the AXI protocol independently.

    Does the above answer your question?

    Xingguang

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