CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM


hi, experts: 

In Cortex-A57 TRM chapter 4.3.66 :

It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1.

Its name is S3_1_C15_C2_0.

Why?

best wishes,

hi

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  • The CPUACTLR_EL1 (and CPUECTLR_EL1 and CPUMERRSR_EL1) are implementation defined registers.

    The ARMv8 architecture defines a number of system registers that a processor must implement (e.g. SCTLR_EL1).  It also leaves encoding space for processors specific (or IMP DEF) registers.  A processor designer can choose how many IMP DEF registers they want their processor to include, what to use them for and what to call them. 

    The ARM assembler (armasm) recognizes the name architectural registers.  BUT not the IMD DEF registers, for these you have to give the encoding.

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  • The CPUACTLR_EL1 (and CPUECTLR_EL1 and CPUMERRSR_EL1) are implementation defined registers.

    The ARMv8 architecture defines a number of system registers that a processor must implement (e.g. SCTLR_EL1).  It also leaves encoding space for processors specific (or IMP DEF) registers.  A processor designer can choose how many IMP DEF registers they want their processor to include, what to use them for and what to call them. 

    The ARM assembler (armasm) recognizes the name architectural registers.  BUT not the IMD DEF registers, for these you have to give the encoding.

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