Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
Processors
Jump...
Cancel
Processors
Cortex-A / A-Profile forum
ARM Cortex-A9 | Non-cacheable memory range
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
Replies
9 replies
Subscribers
273 subscribers
Views
10765 views
Users
0 members are here
Cortex-A9
Cortex-A
Memory
Related
ARM Cortex-A9 | Non-cacheable memory range
Offline
S R Chidrupaya
over 7 years ago
Note: This was originally posted on 23rd May 2013 at
http://forums.arm.com
Hi all,
I am designing an application on xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).
For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?
Thanks
John
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
Regarding Visibility of Multi Master ACE-Lite System
0
11911
views
1
reply
Latest
2 months ago
by
Zhifei Yang
Not Answered
The certification for the development of Trusted Applets
0
OP-TEE
Trusted Execution Environment (TEE)
TrustZone
9861
views
1
reply
Latest
2 months ago
by
Zhifei Yang
Not Answered
Core_n System Timer reset behaviour
0
Cortex-A35
Armv8-A
9830
views
1
reply
Latest
2 months ago
by
Zhifei Yang
Answered
Use Cortex-A53 Cryptography Extension to optimize crypto operations.
+1
7822
views
1
reply
Latest
2 months ago
by
Zhifei Yang
Answered
why descriptions of SAU_RLAR is different in two user duides?
0
Armv8.1-M
Cortex-M33
4619
views
6
replies
Latest
2 months ago
by
Harland
<
>
View all questions in Cortex-A / A-Profile forum