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ARM Cortex A5 -Issue: Undefined Instruction when write/read value of CNTFRQ register in core ARMv7

Dear ARM expert,

I'm new to ARM. I am trying to use generic timer, but seems CNTFRQ register can be accessed.

I saw the description in the ARM (Architecture Reference Manual) for the ARMv7-A and ARMv7-R:

" To access CNTFRQ, software reads or writes the CP15 registers with <opc1> set to 0, <CRn> set to c14, <CRm> set to c0, and <opc2> set to 0. For example:
   MRC p15, 0, <Rt>, c14, c0, 0 ; Read CNTFRQ into Rt
   MCR p15, 0, <Rt>, c14, c0, 0 ; Write Rt to CNTFRQ " 

My code is:

    static inline uint32_t read_cntfrq(void)
      {
          uint32_t frq;

          asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(frq));
          return frq;
      }

    static inline uint32_t write_cntfrq(uint_32 cntfrq)
     {

        asm volatile("mcr p15, 0, %0, c14, c0, 0" :: "r"(cntfrq));
     }

I had just follow up the guide, but i can't write/read value of CNTFRQ register. It always return fault: "Undefined instruction handlers".

Note: I have use kit Sama5d2Xplained , I use sama5d2 software package for getting started.

I had adjusted the fault image as below:

Parents
  • The Cortex-A5 doesn't support the Generic Timer.  Support was first added in the Cortex-A7 and Cortex-A15, the generation after the Cortex-A5.  Software can check whether the Generic Timers are present by reading ID_PFR1

    The Cortex-A5 does include a set of timers, but they are memory mapped.  You can find details of the programming interface within the Cortex-A5 MPCore's TRM.

Reply
  • The Cortex-A5 doesn't support the Generic Timer.  Support was first added in the Cortex-A7 and Cortex-A15, the generation after the Cortex-A5.  Software can check whether the Generic Timers are present by reading ID_PFR1

    The Cortex-A5 does include a set of timers, but they are memory mapped.  You can find details of the programming interface within the Cortex-A5 MPCore's TRM.

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