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Page Table Indexing using Virtual Address bits

Amitra29877

Hello Experts,

In section G5.5.1 " Overview of VMSAv8-32 address translation using Long-descriptor translation tables" of ARM ARM and also in the code which I got from repository, I can see bits [31:30] of VA are used to index level 1 table.

Code:

//Traverse the virtual-address in 1st level pagetable
//Only bit 31:30 use for 1st level addressing
addr_1stLevel = (virtualAddress & 0xC0000000);

//Get the index from virtual address
addr_1stLevel = (addr_1stLevel >> 30);

//Get the address on the address
addr_1stLevel = (addr_1stLevel << 3) + baseAddress;

ARM ARM:

I am trying to understand why VA[31:30] are used to index level 1 table ? And bits 29:21 are used to index level 2 table ? 

I was considering ARM ARM as a general example. But I could see the same is implemented in code. 

Can anyone explain the logic behind indexing tables with these specific bits of VA ?

Regards,

Amitra

Parents
  • +1

    I do not know the real reason, that's the designer choice I guess.

    But the reason for different tables is (likely) to save memory for the tables.

    If you would like to have one table for the whole 4GB with 4KB pages, you will need 1M entries, each 8 bytes, so 8MB for the page table. But most of the entries will be just empty.

    So you split it up. First (design choice I guess) you have a table with an entry for each 1GB.  If this choice is also driven by silicon design or just to reduce memory needs is out of my knowledge.

    Anyway; why do you want to know this?

Reply
  • +1

    I do not know the real reason, that's the designer choice I guess.

    But the reason for different tables is (likely) to save memory for the tables.

    If you would like to have one table for the whole 4GB with 4KB pages, you will need 1M entries, each 8 bytes, so 8MB for the page table. But most of the entries will be just empty.

    So you split it up. First (design choice I guess) you have a table with an entry for each 1GB.  If this choice is also driven by silicon design or just to reduce memory needs is out of my knowledge.

    Anyway; why do you want to know this?

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