Hi all,
I'm trying to configure a Coresight Trace Memory Controller (in ETB configuration) for my Cortex A9 processor through JTAG. I have a question regarding the state machine in the white paper: it says the initial state after RESET is the Disabled state, in which the module can be programmed. However, in the register definitions, it shows the reset value of the Status (STS) register as 0xC - which means the TMCReady bit is cleared, meaning that both the TMCEnable and TMCReady bits are 0 - which can only be true in the disabling state.
How does the TMC transition to the disabled state? However long I wait, the TMCReady bit does not get set, so it never enters the disabled state.
Kind regards,
Jan