I have a question regarding the synchronization of caches on ARMv8 on Multi-Core.
Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes.
The 2 cores did cache a line from RAM:
Then, each core did write 1 byte in that line:
If at this point both cores did flush L1, will the resulted line in RAM will be like this:
Or, the data will be corrupted, and only 1 of the 2 bytes will be written in RAM?
I did try that on i.MX8QXP (Quad Core, ARM CortexA35) with a bare-metal test, and surprisingly, I didn't find a corruption.
Does this mean that the cache keeps track of which byte in the Line did change? Or, my test wasn't synchronized enough and I should get a corruption?
Just to add to the earlier reply. Software would need to mark the region containing this address as "shareable". This tells the core that other cores/masters access the location and that hardware coherency needs to be maintained.