In a GICv3 based system, is it possible to have the following configuration:
While running NS-EL1/EL0:
-NS Group1 interrupts triggered as IRQ to NS-EL1
-Secure Grp1 interrupts routed as FIQ to EL3
-Secure Grp0 interrupts routed as FIQ to EL3
This is achieved with SCR_EL3.IRQ=0 / SCR_EL3.FIQ=1
While running S-EL1/EL0:
-Secure Grp1 interrupts routed as IRQ to S-EL1
-NS Grp1 interrupts triggered as FIQ to S-EL1
-Secure Grp0 interrupts routed as FIQ to EL3 (?)
Considering SCR_EL3.IRQ=0 / SCR_EL3.FIQ=0, it does seem to make both Secure Group0 and Secure Group1 FIQs trapped into S-EL1?
I wonder if it needs to provision a special logic in S-EL1 to forward the Group0 interrupt to EL3?
In other words, isn't it possible to discriminate the target exception level for secure Grp0 and secure Grp1?
Also I noticed a "Routing Modifier" bit in the aarch64 gic interface control register, would this help solving such case?
Thanks & Regards.
Short answer is "no" I'm afraid.
While in S.EL0/1, the GIC will use IRQs for S.G1. With NS.G1 and G0 being sent as FIQs. FIQs are either routed to EL3, or they are not. You can't route a subset of FIQs to EL3.
Thanks Martin, things got clearer now.